Various examples of the fabrication of P channel and N channel organic transistors (OTFT) through deposition processes using a chemical vapor or solution, onto glass, silicon, or substrates of organic polymers, as described in Tsumura, A.; Koezuka, K.; Ando T.: Macromolecular electronic device: Field-effect transistor with a polythiophene thin film. Appl. Phys. Lett., 1986, 49, 1210, Kwon, J.-H.; Seo, J.-H.; Shin, S.-I.; Kim, K.-H.; Choi, D. H.; Kang, I. B.; Kang, H.; Ju, B.-K.: A 6,13-bis(Triisopropylsilylethynyl) Pentacene Thin-Film Transistor Using a Spun-On Inorganic Gate-Dielectric, IEEE Trans. On Electron Devices., 2008, 55-2, 500-505, and Yan, H.; Chen, Z.; Zheng, Y.; Blache, R.; Newman, C.; Lu, S.; Woerle, J.; Facchetti, A.: Solution Processed Top-Gate n-Channel Transistors and Complementary Circuits on Plastics Operating in Ambient Conditions, Adv. Materials, 2008, 20, 3393-3398, are known in the art. For practical applications, a fabrication process provides a method for electrically connecting elements of an integrated structure of an OTFT formed in different conducting layers at different levels of the multilayered stack. For example, vertical interconnections may be realized from a first level, in which there may be source and drain contacts of one or more OTFT, to a second level in which there may be gate contacts of one or more OTFT. In other words, it is desirable to connect circuit nodes or contacts on a same level with those on different levels, thereby realizing vertical interconnections that go from a lower level conductive region or to an upper level of metal contacts (so called “vias” or “via holes”) crossing one or more dielectric layers of the multi-layer integration stack.
In this way it is possible to realize complex devices, such as logic gates, that are building blocks of memory devices, of data processing units (ALU and microprocessors), driving systems for various types of devices, such as sensors and actuators and alikes.
Vertical interconnections or vias are typically realized inside vias holes formed through the polymeric material of isolation dielectric layers, using an appropriate definition technique such as Ink Jet Printing (IJP), Laser Ablation (LA) and Reactive Ion Etching (RIE). In the first case, a solvent is used to dissolve the polymeric material locally through an IJP deposition, as described in Takeo Kawase et al.: Inkjet Printed Via-Hole Interconnections and Resistors for All-Polymer Transistor Circuits, Adv. Mater. 2001, 13, No. 21, November 2. In the second case, via holes are formed by ablation of the polymeric material, that is using a laser beam that, through apertures of a mask, vaporizes away the polymeric material producing a certain number of via holes, as described in U.S. Pat. No. 6,259,148—Modular high frequency integrated circuits structure issued on Jul. 10, 2001 In the third case, a mask is formed by photolithography over the surface of the layer of polymeric material, and thence a RIE etching, typically oxygen-based RIE is carried out, through the apertures of the mask as described in I. Mejia et. A.: Improved Upper Contacts PMMA On P3HT PTFTS Using Photolithographic processes, Microelectronics Reliability 48, 2008, 1795-1799.
After having realized the via holes, two different approaches may be used for filling them with a conducting material, realizing in this way the vertical interconnections. The first approach involves a localized deposition by IJP, inside the holes, of a functional ink based on a polymeric conducting material, such as the so called PEDOT:PSS (Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate)), or of an equivalent ink jet printable fluid material, such as a colloidal suspension of metal nanoparticles, or a colloidal suspension of an organometallic salt or compound. In case of use of colloidal suspensions of metal nanoparticles, generally gold and/or silver nanocluster are used, passivated by organic agents such as thiols, amines, or phosphines with a long hydrocarbon chain for keeping the suspension of nanoparticles homogeneous and hindering early undue aggregation phenomena to bulk metal. Generally, in the case of inks based on metal nanoparticles as well as in case of solutions of metal precursors, deposition of the ink is followed by a heat, UV, or laser irradiation treatment, for decomposing the organic component of the fluid ink and favor sintering of metal nanoparticles or inducing their formation from the precursor compound and successively promoting the coalescence into bulk metal as described in Daniel Huang et al. Journal of The Electrochemical Society, 150 (7) G412-G417 2003; Sawyer B. Fuller et al. Journal Of Microelectromechanical Systems, Vol. 11, No. 1, February 2002, 54-60; N. R. Bieri, et al. Appl. Phys. Lett., Vol. 82, No. 20, 19 May 2003, 3529-3531; Jaewon Chung, et al. Appl. Phys. Lett., Vol. 84, No. 5, 2 Feb. 2004 pp 801-803; Jai Joon Leea, et al. Journal of Ceramic Processing Research. Vol. 8, No. 3, 2007, 219-223; K. F. Teng, et al. Ieee Transactions on Components Hybrids, and Manufacturing Technology, vol. Chmt-12, No. 4, 1987.
Upper electrodes in contact with the vertical interconnections generally are made by IJP deposition of the same material with which the vias are made as described in T. Kawase. Et al. IEEE IEDM 2000, 623-626; A. Knobloch, et al. IEEE Session 4: Polymer Electronic Devices II, 84-90. Definition of upper electrodes by IJP printing limits the scalability of devices. As a matter of fact, the minimum dimension that may be obtained in general with localized deposition techniques is around 20 μm. Therefore, the printing techniques of definition of planar conducting structures, particularly the upper electrodes of integrated structures of organic transistors (OTFT), imply constraints of minimum line width of the particular printing technique that is used.
In the cases in which this limit to scalability is unacceptable, instead of localized deposition with a printing technique, a “soft” metal deposition technique is used producing a massive metallization of the surface of the stack such to completely fill the vias holes of vertical interconnections and form a superficial metallization layer without discontinuities, that is successively lithographically printed to define the upper electrodes and lines of electrical connection of the device. A drawback of this technique is that there is a considerable waste of metal and the risk of damaging delicate organic layers of the stack during the prolonged (heavy) metal deposition and/or during the etching of the metal layer.